Researchers at the Chipworks Process Analytical Laboratory performed a process anatomy of the Xilinx Kintex-7 FPGA chip fabricated using TSMC's 28nm HPL process (based on gatelast HKMG technology), which is an analysis report.
Since we have analyzed the two products of the 45nm Xeon processor and the 32nm Westmere processor which were produced by the gatelast HKMG process in the past two generations of Intel, we will of course compare the similar products of TSMC with this one. Similarly, we also We will review the results of our analysis of the Uniphier chip made by Panasonic using the gatefirst HKMG process last fall.
TSMC Gate last HKMG 28nm HPL Process Products: Xilinx Kintex-7 Let's start with Xilinx's Kintex-7 FPGA products! The Kintex family of products is the mid-range product of the recently introduced 28nm process 7 series FPGA chip from Xilinx. The design appeal of this series is to achieve the highest performance-price ratio and maintain the performance of the chip similar to its predecessor Virtex-6 product, but The price is reduced to about half of the former.
As shown in Figure 1, the Kintex-7 series uses an 11-layer metal interconnect layer design, in which the 1x layer has a 1-4th metal layer with a pitch of about 96nm, which is the pitch we have seen so far. The smallest product.
Longitudinal section of Xilinx Kintex-7 FPGA product interconnect layer According to our preliminary analysis results, the contact gate pitch is 118nm, and the minimum gate length is about 33nm. Of course, due to the adoption of replacement gate technology. We can't accurately know the width of the original polysilicon dummy gate, and this width is the important size that is really used to define the drain and source in the self-aligned process.
The top view of Figure 2 shows that TSMC has adopted stricter circuit layout design guidelines in this chip. In the past debates about the advantages and disadvantages of gatefirst and gatelast, similar topics have been frequently mentioned. It can be seen that this product adopts a one-way layout (the so-called 1D Layout, the circuit image only extends in the same direction, in contrast to the Manhattan layout, commonly known as 2D Layout, the image can be horizontal And vertical extension), and a number of virtual gates are used to ensure lithographic dimensional variability. However, this one-way layout has a degraded circuit density compared to the Manhattan layout. [[wysiwyg_imageupload:189:]] Figure 2 The top view of the gate and the active layer. From the outside, the chip seems to use dual imaging technology in the manufacturing process, and the Cut mask is applied. The image in the vertical direction cuts the image in the horizontal direction). Since the layout flexibility of FPGA chips is usually better than that of logic chips, the layout of a large number of virtual gates and virtual active areas is used in this chip.
3-HKMG gate structure analysis: In terms of gate structure, TSMC's 28nm process products have some similarities with Intel 45nm process products.
The gates of both products use the same manufacturing steps as follows:
1- First, a buffer oxide layer at the bottom of the gate is formed. The presence of this layer protects the High-k gate insulating layer; 2- then deposits a High-k gate insulating layer; 3- Deposits a PMOS/NMOS general work function metal layer ( Generally, the TIN material is mainly used; 4) then depositing a polysilicon sacrificial gate; 5- drain-source ion implantation using a self-aligned process, drain-source high-temperature annealing; 6-depositing the interconnect dielectric layer, and performing The planarization process is performed until the top of the polysilicon gate is exposed; 7-polysilicon sacrificial gate etching; 8-PMOS/NMOS metal gate is formed and planarized.
It can be seen that the High-k first+gate last HKMG process used in Intel 45nm process products is similar (Intel 32nm process products have been upgraded to High-k last+gate last process), and TSMC 28nm HPL products also use High-k first-gate. Last process.
Of course, there are some differences between the two, mainly in the following points:
1- TSMC does not use embedded SiGe silicon strain technology in this chip; 2- TSMC has a thick high-density metal layer in the PMOS gate of this chip, but there is no similar structure in Intel products; 3- The TSMC chip has no dielectric layer structure on the top of the gate. The sidewall structure of the 4-chip IC chip is different from that of Intel. It should have the function of fine-tuning the drain source.
In the past, Intel has claimed that metal gates and contact structures can be used in NMOS transistors to stress the channel of the NMOS transistor; we speculate that TSMC may have a similar technique, but the position of its contacts is far from the edge of the gate. Obviously larger, less likely to produce stress. On the other hand, we do not see the use of special strain techniques on the PMOS tube, so the strain technique used in the PMOS tube (if it is used) is unknown. Of course, the thicker high-density metal layer in the PMOS gate may be There is a function of forming stress.
However, don't forget that this chip uses a 28nm HPL process, and this level of process generally does not require the current drive capability of the tube to be as high-performance as HP. Therefore, embedded silicon is not used in this level of process.é”— Technology.
Detailed analysis of this product is currently in progress, and readers who need more details can refer to this link.
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