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Abstract: In view of the characteristics of ISD voice chip, a voice circuit controlled by single-chip microcomputer and capable of cyclic recording and playback is designed. It can be used as a recorder, repeater and audio recorder, which saves storage space and reduces cost. It has high practical value. .
Keywords: ISD4004 voice loop recording and playback
At present, the solid-state recorders and various recorders on the market mostly use sequential recording, and do not have the function of loop recording. Once the memory is full, it must be re-operated. This paper solves the above problems by designing a voice circuit capable of cyclic recording and playback.
1 device function introduction
The ISD series of voice chips is a product launched by the US ISD company. This series of voice chips adopts the patented technology of multi-level direct analog memory (Chip Corder). The sound does not need A/D conversion and compression. Each sample value is directly stored in the on-chip flash memory without A/D conversion error. Therefore, voice, music, and sound effects can be reproduced in a true and natural manner. The quantization noise and metal sound caused by the quantization and compression of the general solid-state recording circuit are avoided.
figure 1
The ISD4004 voice chip uses CMOS technology and includes a crystal oscillator, anti-aliasing filter, smoothing filter, automatic squelch, audio power amplifier and high-density multi-level flash memory array (see Figure 1), so it only needs to be very A small number of peripheral devices can form a complete sound recording and playback system. The chip design is based on all operations controlled by the microcontroller, and operational commands are sent via the serial communication interface (SPI or Microwire). The sampling frequency can be 4.0 Hz, 5.3 Hz, 6.4 Hz, 8.0 kHz. The lower the frequency, the longer the recording and playback time, and the sound quality is reduced. The on-chip information is stored in the internal flash memory, and can be stored for 100,000 (typical) repeated recordings for 100,000 times in the event of a power failure. The device operates at 3V, operates at 25 to 30mA, maintains a current of 1μA, and has a single-chip recording and playback time of 8 to 16 minutes. It has good sound quality and is suitable for use in mobile phones and Other portable electronic products.
1.1 Pin Description
The pin diagram of the ISD4004 series chip is shown in Figure 2.
figure 2
   In-phase analog input (ANA IN+) - This is the non-inverting input of the recorded signal. The input amplifier can be driven either single-ended or differential. For single-ended input, the signal is input by the coupling capacitor. The maximum amplitude is 32mV. The coupling capacitor and the 3kΩ input impedance of the local terminal determine the low-end cutoff frequency of the chip frequency. In differential driving, the maximum amplitude of the signal is 16mV peak-to-peak.
Inverting analog input (ANA IN-) - differential drive, this is the inverting input of the recorded signal. The signal is input through the coupling capacitor, the maximum amplitude is 16mV peak-to-peak, and the nominal input impedance of the local end is 56kΩ. When single-ended driving, the local terminal is grounded through the capacitor. In both modes, the coupling capacitance values ​​of the ANA IN+ and ANA IN- terminals are the same.
Audio Output (AUD OUT) - Provides an audio output that can drive a 5kΩ load.
Chip Select (SS) - This side is low, that is, the ISD4004 series is selected.
Serial Input (MOSI) - This is a single-line input. The master should place the data on the local side for ISD input half a cycle before the rising edge of the serial clock.
image 3
   Serial Output (MISO) ISD-serial output. When ISD is not selected, the local end is in a high impedance state.
Serial Clock (SCLK) - The clock input of the ISD, which is generated by the controller and used to synchronize the data transfer between MOSI and MISO. Data is latched to the ISD on the rising edge of SCLK and out of the ISD on the falling edge.
Interrupt (INT) - The local end is an open-drain output. When the ISD detects EOM or OVF in any operation (including fast-forward), the local end goes low and remains. The interrupt status starts to clear in the next SPI cycle, and the interrupt status is also available. The RITN instruction reads.
Row Address Clock (RAC) - Drain Start Output. A RAC cycle indicates that the operation of the ISD memory has been performed one row (the memory in the ISD4004 series has 2400 rows). For devices with a sampling frequency of 8 kHz, the RAC period is 200 ms, of which 175 ms is maintained at a high level and a low level is at 25 ms. In fast-forward mode, RAC is 218.75μs high and 31.25μs is low. This terminal can be used for storage management technology.
External clock (XCLK) - There is an internal pull-down component on the local end. The internal sampling clock of the chip is calibrated at the factory. The error is within +1%. When no external clock is connected, this terminal must be grounded.
The automatic squelch (AM CAP)-1μF capacitor forms part of the internal peak detection circuit. The detected peak level is compared with the internally set threshold to determine the operation of the automatic squelch circuit. The automatic squelch circuit does not attenuate when the signal is large, and the attenuation is 6dB when muting. At the same time, the 1μF capacitor also affects the response speed of the signal amplitude in the automatic squelch circuit. The terminal is connected to VCCA to disable automatic squelch.
   1.2 Serial External Interface (SPI)
The ISD4004 operates on the SPI serial interface. The SPI protocol is a synchronous serial data transfer protocol that assumes that the microcontroller's SPI shift register operates on the falling edge of SCLK. Therefore, for the ISD4004, the MOSI pin data is latched on the rising edge of the clock and the data is sent to the MISO pin on the falling edge. The details of the agreement are as follows.
1 All serial data transfers begin on the falling edge of SS.
2SS must be held low during the transfer and held high between the two instructions.
3 Data is shifted in on the rising edge of the clock and shifted out on the falling edge.
4SS goes low. After inputting the command and address, the ISD line starts to play and hold.
The 5 instruction format is an 8-bit control code plus a 16-bit address code.
Figure 5
   Any operation of the 6ISD (including fast forward) generates an interrupt if it encounters EOM or OVF, and the interrupt status is cleared at the beginning of the next SPI cycle.
7 When the “read†instruction is used to shift the interrupt status out of the IISO MISO pin, the control and address data are also shifted in from the MOSI side.
8 All operations start when the run bit (RUN) is set to 1, and end when set to 0.
   9 All instructions start executing on the rising edge of the SS side.
   The OVF flag indicates that the ISD recording and playback operation has reached the end of the memory. The EOM flag is only set when the internal EOM flag is detected during playback, as shown in Figure 3.
The following is a list of the order in which the ISD devices are operated.
Figure 6
   * Information is fast forward. Users don't have to know the exact address, they can skip a message quickly. Information fast forward is only used in playback mode. The playback speed is 1600 times normal. After the EOM is stopped, the internal address counter is incremented by 1, and the next message is taken.
* Power-on sequence. When the device is delayed by TPUD (8kHz) sampling, it will take about 25ms to start operation. Therefore, after the user sends a power-on command, they must wait for the TPUD to issue an operation command. For example, playback from 00 should follow the following sequence: send power up command; wait for TPUD (power-on delay); send a SETPLAY command with address value 00; send PLAY command. The device will start playing from the 00 address. When the EOM appears, it will be interrupted immediately and the playback will stop. If recording from 00, press the following sequence: send power up command; wait for TPUD (power-on delay); send power up command; wait 2 times TPUD; send SETREC command with address value 00; send REC command. The device starts recording from the 00 address until the OVF (end of memory) appears and the recording stops.
1.3 Timing
The 8-bit and 24-bit command formats are shown in Figures 4 and 5.
Recording, playback, and stop timing are shown in Figure 6.
Figure 7
2 cycle recording and playback circuit design
The circuit adopts AT89C51 single-chip microcomputer, realizes function conversion by operating five micro-button switches and one micro-switch, and the operation command is sent by serial communication interface (SPI). The circuit can work in sequential mode and in cyclic mode. When working in loop mode. When working in the recording mode of the loop mode, the ISD chip will always record the last 16 minutes of voice information until the stop button is pressed.
2.1 hardware circuit design
The circuit schematic is shown in Figure 7. The whole circuit is controlled by a single-chip display circuit. The ISD4004 voice recording and playback circuit, microphone input circuit, and audio power amplifier circuit are composed of several parts. The chip select signal SS of the ISD4004 is provided by the controller P2.0. The serial port of the AT89C51 of the single-chip microcomputer works in the synchronous shift register mode. The synchronous shift pulse is output from TXD (P3.1) to the serial clock input terminal SCLK of ISD4004, and the data is input and output by RXD (P3.0). Because the AT89C51 microcontroller does not have a (SPI) interface, the RXD (P3.0) data line is multiplexed through a three-state gate. For the microcontroller, it is output as an output to the serial input (MSI) of the ISD4004; as an input, it is connected to the serial output (MISO) of the ISD4004. The pull switch Ks in the circuit is used to select whether to enable or cancel the loop recording function.
2.2 Software Design
The entire program consists of two parts: the main program and the interrupt subroutine. The AT89C51 microcontroller provides the user interface for the keyboard, display and ISD4004. It receives the keystrokes and passes the corresponding commands to the ISD4004 while monitoring the interrupt output of the ISD4004. When the switch KS is closed (KS = 1), the status register of the ISD4004 is read, and corresponding processing is performed according to the states of the OVF and the EOM. When OVF=1, that is, the memory overflows, the address of ISD4004 is set to zero regardless of the current state, and the original instruction is continued; when EOM=1, the current state may only be playback or fast forward, if fast The input is placed in the playback state and continues to run. This design realizes the function of loop recording and playback, and at the same time, when fast forward, it automatically stops at the beginning of the next speech segment and continues to play.
The interrupt program flow chart is shown in Figure 8. A list of source programs can be found at
3 overall performance and function expansion
The power consumption of the circuit is 200mW during normal operation, and the power consumption increases when the volume is increased. The whole circuit works stably and reliably, the output sound is clear, the sound is beautiful, and the intermittent sound generated by zeroing the ISD address in the loop mode can not be heard subjectively. The maximum recording and playback time of the system is 16min. If you need to increase the recording and playback time, you only need to increase the number of ISD4004 chips, which can be achieved by chip selection. For example, with four ISD4004s, you can achieve nearly one hour of recording length.
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