In recent years, especially after 9/11, the demand for video surveillance in various occasions has become increasingly strong, and in the same occasion, it may be necessary to monitor multiple targets at the same time, which gives us the requirement to reduce the cost of single-channel video processing as much as possible. Completing as many digital video compression processes as possible with a single DSP processor will undoubtedly be an effective way to reduce the cost of single-channel video surveillance. Fortunately, with the continuous improvement of DSP processing performance and the further optimization and maturity of the embedded digital video codec algorithm, it is possible to complete up to eight CIF format digital video compression processing by a single DSP. This article uses TI's latest Davinci series DSP TMS320DM6437 and Xilinx's high-performance, low-cost Spartan-3 series FPGA to build a high-performance, low-cost embedded multi-channel video surveillance system hardware platform.
Embedded multi-channel video surveillance system hardware platform system
In order to reduce the single-channel cost of the embedded video surveillance system as much as possible, it is undoubtedly a direct and effective method to reasonably select a DSP processor to complete as many digital video compression processing as possible. TI's latest Davinci series DSP is optimized for digital media applications. It is an upgraded product based on the well-known TMS320DM642 digital media processor, which has been widely used. The processing performance is further improved and the on-chip peripherals. More suitable for the requirements of video processing systems, the TMS320DM6437 is a representative of high performance and low cost. In this paper, it is selected as the main processor of the embedded multi-channel video surveillance system. Under the condition that the digital video encoder algorithm is optimized and reasonable, it can realize the H.264 encoding processing of 8-channel CIF format.
However, the TMS320DM6437 has only one digital video input interface. In order to interface the 8-channel video decoder, it is necessary to add coupling logic between the video decoder and the video input interface of the TMS320DM6437. The high-performance, low-cost, programmable FPGA can easily realize the two. The coupling logic between. In addition, the FPGA is rich in resources that can be used to implement certain image processing functions, such as image size scaling, anti-glare, and so on.
The system block diagram of the DSP + FPGA embedded multi-channel video surveillance system hardware platform constructed by this is shown in Figure 1.
Figure 1 DSP+FPGA multi-channel video surveillance system hardware platform
Overview of TMS320DM6437
The TMS320DM6437 is a 32-bit fixed-point DSP developed by TI in 2006 for high-performance, low-cost video applications with a frequency of 600MHz. TMS320DM6437 has the following features:
TMS320C64x+ DSP core with TI's 3rd generation ultra-long instruction set structure (VelociTI.3), clocked at up to 600MHz, supports 8 8-bit or 4 16-bit parallel MAC operations, peak processing capability up to 4800MIPS, real-time processing 8 Road CIF or 3-way D. format H.264 encoding algorithm.
A 2-level Cache memory architecture with on-chip 32K bytes of RAM/Cache configurable level 1 program memory L1P, 48K bytes of RAM + 32K bytes of RAM/Cache configurable level 1 data memory L1D, and 128K bytes of RAM /Cache configurable level 2 program / data memory L2, the memory architecture is more flexible and reasonable, which is conducive to improving the throughput of image processing code / data.
On-chip 64-channel enhanced DMA controller EDMA3, which supports the transmission of complex data types, is conducive to efficient transmission of image data and format conversion.
Rich external memory interface: A dedicated 32-bit, 200MHz, 256M byte addressable DDR2 memory interface for high-speed, high-capacity DDR2 memory for storing code and data; an 8-bit, 64M byte addressing The spatial asynchronous memory interface is used to interface 8-bit Nor Flash or Nand Flash to store the firmware code.
Rich on-chip peripherals: a dedicated single-channel video input interface that can easily interface with a variety of digital video input standards, as well as common video pre-processing functions; a dedicated single-channel video output interface that provides multiple An analog video output standard, can also provide a variety of digital video output standard interface, and also support multiple video window management and superimpose text data on the video screen before the video output; a multi-channel audio serial port, seamless interface audio Codec device, which realizes the input/output of analog video signal; an I2C bus, which can seamlessly interface the video decoder/encoder and the audio codec control port to facilitate the control of the audio/video codec; 32-bit PCI bus, convenient Interface with the PC to achieve multi-board parallel operation. 10/100M Ethernet MAC for easy implementation of embedded video networking requirements; 16-bit HPI interface for easy implementation of dual-processor video processing system with master/slave structure.
As can be seen from the above, the DM6437 is very suitable as a main processor for a single channel video processing system. In order to make the DM6437 suitable for multi-channel video surveillance systems, it is necessary to combine the data of multiple video channels and then input them through the DM6437 on-chip video input interface. Therefore, the following will focus on the on-chip video input/output interface of the DM6437.
DM6437 Video Subsystem VPSS
The DM6437 on-chip video input/output interface is collectively referred to as the video subsystem VPSS. The video subsystem of the DM6437 consists of two parts. The first is the video processing front end, which is used to input digital video data and provide interfaces for various standard digital video inputs. The input digital video data is preprocessed as necessary. The second is the video processing backend for outputting digital video data to drive the display to display video images.
The DM6437 video processing front-end VPFE provides two functions for the video processing system. One is to provide a seamless interface for multiple standard digital video inputs, and the other is to provide the necessary pre-processing for various video processing applications.
The DM6437 digital video input interface is called a CCD controller and provides a data path and necessary synchronization signals for the input digital video stream. Its functions are as follows:
*16-bit video data bus
*Pixel clock frequency up to 75MHz
* Direct interface to CCD or CMOS image sensor
* Can interface 8/10 bit BT.656 standard digital video stream
* Can interface 8/16-bit YCbCr 4:2:2 format digital video stream with line and field sync signals
For video surveillance applications, the video signal is typically an analog video signal from a camera that is converted to 8/10-bit BT.656 or 8/16-bit YCbCr 4:2 with line and field sync signals via a video decoder: 2 digital video stream, and then input to the DSP for processing.
To accommodate a variety of video processing applications, the DM6437's video front end also offers the following three pre-processing functions: Previewer Previewer: Converts RGB image formats from CCD controllers or from external memory to YCbCr 4:2:2 image format.
Scaler Resizer: accepts video data from the previewer or text memory. The image size is scaled by hardware. The horizontal and vertical scales are independent of each other, and the zoom range is 1/4x~4x.
H3A: Autofocus, auto white balance, and auto exposure are implemented by hardware. First accept the RGB image format, and subdivide the image into two-dimensional pixel blocks, the size and position of the pixel block can be programmed. The pixel blocks are then accumulated and peaked. Finally, the 3A control output is implemented.
The DM6437 video processing backend VPBE is used to implement the output display of video images. An image on the display can be divided into several areas, each of which can represent a different video source, ie from a different video output buffer, before the output display, the video data from different video output buffers needs to be combined into A complete digital video stream, this process is called video window management; in addition, it is often necessary to superimpose certain graphics, characters and other information onto the video image to output the display. The graphics and characters superimposed on the video image are stored in independent. In the buffer, therefore, before the output is displayed, the data from the graphics and character buffers needs to be combined into the output digital video stream. This process is called graphics, character OSD window management and overlay. Finally, the composited full digital video stream is output in a certain timing format. This process is called video output coding. The DM6437 video processing backend can support 2 video windows and 2 graphics and character OSD window management at the same time, and can support 8 video window and OSD window data overlay methods. The DM6437's video output encoding enables standard analog video output for direct drive analog monitors as well as multiple standard digital video outputs for direct drive display with digital interface.
For video surveillance applications, the video output is generally used to preview the video input of a channel, which is displayed by the analog monitor, so it can be realized directly with the analog video output of the DM6437.
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