Abstract : EtherCAT is a real-time industrial Ethernet protocol. Link redundancy technology is an important means to achieve link stability and reliability. This paper introduces the principle of FPGA-based EtherCAT link redundancy, and designs the automatic switching between the communication link and redundant link between the master station and the slave station, the slave station and the slave station through FPGA, thus realizing the link redundancy of EtherCAT. . The feasibility of this method is verified by testing, which increases the reliability and maintainability of the EtherCAT system.
0 PrefaceEtherCAT was originally developed by Beckhoff in Germany based on standard Ethernet technology and is a technology with flexible network topology [1]. EtherCAT technology has the advantages of fast speed, good synchronization performance, support for multiple topologies, standard Ethernet frames, and high bandwidth utilization [2]. Redundancy technology in industrial Ethernet is one of the most effective means to improve the reliability and maintainability of Ethernet systems [3]. Link redundancy is a remedy for responding to network port failures (including failure and connection of the primary network card itself) and link failures (referring to disconnection of links between slave nodes, such as network cable disconnection). In the case of relatively high requirements for stable system operation, link redundancy technology is required. Link redundancy is a single fault-tolerant mechanism that keeps data transmitted with each slave if the link fails at some point. The main communication direction will also resume when communication resumes. If there is a communication interruption in more than one place, all must be restored before another error occurs. In [4], an industrial Ethernet EtherCAT redundancy and hot-swap technology is introduced. This method uses a ring redundancy structure to connect the last ESC node to the primary station. This method can solve single point failure. However, power failure is required during fault repair and cannot solve multiple faults. In order to solve this problem, this paper introduces the link redundancy principle of FPGA-based EtherCAT, and designs the automatic switching between the communication link and the redundant link between the master station and the slave station, the slave station and the slave station through FPGA. EtherCAT's link redundancy is achieved, increasing the reliability and maintainability of the EtherCAT system.
1 EtherCAT principleEtherCAT is a real-time industrial Ethernet technology that uses a master-slave architecture, as shown in Figure 1. The primary station sends an Ethernet frame to each slave station, and the slave station extracts the corresponding data from the data frame by addressing or inserts the data into the data frame, and then transmits the data frame to the next EtherCAT slave. The last EtherCAT slave sends back a fully processed message and the first slave sends it as a response message to the primary station. The main station uses a standard Ethernet interface card or an embedded industrial control computer with an Ethernet interface. The EtherCAT slave uses a dedicated slave control chip ESC to take the receive and forward mechanism. The Ethernet frame can travel in both directions, but only the Ethernet frame. When the incoming packet is sent in the direction of the downlink telegram, the corresponding packet can be processed. If the specified network port is not connected, the ESC automatically returns the Ethernet frame along the original entry.
EtherCAT data uses Ethernet data frames directly, using a frame type of 0x88A4. The EtherCAT data includes 2 B headers and 44 B~1 498 B data. The data area consists of one or more EtherCAT sub-messages, each of which corresponds to a separate device and slave storage area. Each EtherCAT sub-message includes a sub-header, a data field, and a corresponding Work Counter (WKC). After the sub-message is addressed to the slave node and the data is exchanged, the work counter is incremented to record the The processing status of the sub-message. In the sub-message header, the 8-bit command byte specifies the sub-message type (read-write type, addressing type); the 8-bit index number gives the sub-message encoding. The 32-bit sub-message address specifies the operation address for the slave, the addressing type defines the addressing mode; the 8-bit length is used to indicate the number of bytes in the message data area; R is the 4-bit reserved bit; 4 bit M indicates whether the message is the last message; the 16-bit interrupt is currently reserved.
2 FPGA-based link redundancy principleDuring the operation of the EtherCAT communication link, there may be several faults as follows:
(1) The network port is faulty, including the fault and connection of the master station's network card itself.
(2) Link failure refers to the disconnection of the link between the slave nodes, such as the disconnection of the network cable.
In order to increase the reliability and maintainability of the EtherCAT system, redundancy is added between the EtherCAT master and slave links via the FPGA, and each link has a corresponding redundant link as a backup. When link 1 fails, it can automatically switch to redundant link 1 through FPGA; when link 2 fails, it automatically cuts to redundant link 2 through FPGA. In this way, if the link fails at some point, the data can still be transmitted with each slave. When the communication is restored, the main communication direction is also restored, which greatly enhances the stability and maintainability of the system.
As shown in Figure 2, in the block diagram of the EtherCAT master-slave network, the redundancy card is an FPGA-based link redundancy card, which is connected to the host redundant CPU through the communication link 1, and the redundant link 1 and the standby redundant The redundant CPU is connected to realize the redundancy of the active/standby switch between the master and the slave. The communication link 2 is connected to the link 1 of the next-level redundant card, and the redundant link 2 is connected to the redundant link 1 of the next-level redundant card to implement link redundancy of the EtherCAT.
The FPGA implements the automatic switching function of the communication link and the redundant link between the master station and the slave station, the slave station and the slave station.
The present invention provides a method for controlling the temperature of a flue-cured electronic cigarette and a flue-cured electronic cigarette. The flue-cured electronic cigarette includes an N-section heating body, where N is an integer greater than 1, and the heating body is used for heating tobacco. The method for controlling the temperature of the flue-cured electronic cigarette includes: the flue-cured electronic cigarette heats the i-th heating body, and i is an integer greater than 0 and less than N; after the first preset time, the flue-cured electronic cigarette pairs the i+ The first stage heating body is heated; after the second preset time, the flue-cured electronic cigarette stops heating the i-th stage heating body, and continues to heat the i+1th stage heating body. The technical solution solves the problem of unbalanced smoke output of flue-cured electronic cigarettes during multi-stage heating.The present invention provides a method for controlling the temperature of a flue-cured electronic cigarette and a flue-cured electronic cigarette. The flue-cured electronic cigarette includes an N-section heating body, where N is an integer greater than 1, and the heating body is used for heating tobacco. The method for controlling the temperature of the flue-cured electronic cigarette includes: the flue-cured electronic cigarette heats the i-th heating body, and i is an integer greater than 0 and less than N; after the first preset time, the flue-cured electronic cigarette pairs the i+ The first stage heating body is heated; after the second preset time, the flue-cured electronic cigarette stops heating the i-th stage heating body, and continues to heat the i+1th stage heating body. The technical solution solves the problem of unbalanced smoke output of flue-cured electronic cigarettes during multi-stage heating.
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